Design & Performance Analysis of Low Power 1-bit Full Adder at 90 nm node using PTL Logic

This paper explores a new full-adder (FA) cell which works in low power. Here the FA architecture is designed using pass transistor logic (PTL) style with 14 transistors and implemented using Cadence Virtuous Tools in 90 nm technology node. The investigation has been carried out through anatomizing the FA cell into sub modules. The different design metrics are compared with the existing design. The result shows an average power and delay of 1.494 μW and 0.003612 ns respectively, which is less compared with the existing FA.

I. Introduction

In the recent years, with the heavy demand of advanced technology, the designers are working within limited leakage powers specifications to get larger battery life. The designs of these products not only require light weight and slim size, but also low power consumption and fast production to fill up market needs. Almost all battery functioned gadgets like mobile, laptop, tablet, personal digital assistants (PDAs) and ultra-large-scale integration, etc. are designed with better PDP that simultaneously provides assistance to other factor such as chip area, consumption of power, speed of operation, regularity of circuit and long battery life that demand in VLSI [1], [2].