I. Introduction
In recent years, 3-D integration technologies have attracted much attention to overcome performance and scaling problems of large-scale integration (LSI). The 3-D technologies make it possible to fabricate the vertically stacked 3-D LSI with through-silicon vias (TSVs) [1], [2]. The stacking approaches in the 3-D integration processes are well known to be mainly divided into three categories: wafer-to-wafer, chip-to-chip, and chip-to-wafer 3-D stacking [3]–[6]. Especially, the chip-to-wafer 3-D stacking is the most preferable methodology for heterogeneous 3-D integrations because it has higher throughputs and yields due to wafer-level processing and the use of known good dies (KGDs) with various sizes. In order to satisfy the requirements, we have developed massively parallel capillary self-assembly for high-throughput, high-yield, and high-precision multichip alignment/bonding processes using liquid surface tension and hydrophobic/hydrophilic chemistries [7]–[9].