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High-Thermoresistant Temporary Bonding Technology for Multichip-to-Wafer 3-D Integration With Via-Last TSVs | IEEE Journals & Magazine | IEEE Xplore

High-Thermoresistant Temporary Bonding Technology for Multichip-to-Wafer 3-D Integration With Via-Last TSVs

Publisher: IEEE

Abstract:

In this paper, a high-thermoresistant temporary bonding/debonding system using spin-on glass (SOG) and hydrogenated amorphous silicon layers is proposed for the multichip...View more

Abstract:

In this paper, a high-thermoresistant temporary bonding/debonding system using spin-on glass (SOG) and hydrogenated amorphous silicon layers is proposed for the multichip-to-wafer (MCtW) 3-D integration based on a via-last/backside-via through-silicon via (TSV) approach. The shear strengths of chips bonded to wafers through the SOG layers are evaluated. In addition, the debonding performance of the chips from the wafers is investigated by using the KrF excimer laser irradiation. Finally, a via-last/backside-via MCtW 3-D integration process using the temporary bonding/debonding system is demonstrated to show the high feasibility with the successful interconnect formation of a Cu-TSVs daisy chain (10 \mu \text{m} in diameter and 50 \mu \text{m} in depth) with a SiO 2 liner dielectric deposited by O 3 -tetraethylorthosilicate chemical vapor deposition at 350 °C.
Page(s): 181 - 188
Date of Publication: 24 September 2018

ISSN Information:

Publisher: IEEE

Funding Agency:


I. Introduction

In recent years, 3-D integration technologies have attracted much attention to overcome performance and scaling problems of large-scale integration (LSI). The 3-D technologies make it possible to fabricate the vertically stacked 3-D LSI with through-silicon vias (TSVs) [1], [2]. The stacking approaches in the 3-D integration processes are well known to be mainly divided into three categories: wafer-to-wafer, chip-to-chip, and chip-to-wafer 3-D stacking [3]–[6]. Especially, the chip-to-wafer 3-D stacking is the most preferable methodology for heterogeneous 3-D integrations because it has higher throughputs and yields due to wafer-level processing and the use of known good dies (KGDs) with various sizes. In order to satisfy the requirements, we have developed massively parallel capillary self-assembly for high-throughput, high-yield, and high-precision multichip alignment/bonding processes using liquid surface tension and hydrophobic/hydrophilic chemistries [7]–[9].

References

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