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Performance Optimization of Implementation of Lattice Boltzmann Method in ARUZ

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Grzegorz Jahłoński; Joanna Kupis
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Abstract:

The paper presents the performance optimization of implementation of the Lattice Boltzmann method on ARUZ, a massively parallel FPGA-based simulator located in Lodz, Pola...Show More

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Abstract:

The paper presents the performance optimization of implementation of the Lattice Boltzmann method on ARUZ, a massively parallel FPGA-based simulator located in Lodz, Poland. Compared to previous publications, a performance improvement of 46% has been achieved on D2Q9 lattice due to overlapping of communication with computation. The presented approach is suitable also for other cellular automata-based simulations. Extrapolation of results from the single ARUZ board suggests, that LBM simulation of 1080 \pmb×480 lattice on 18 panels of ARUZ would reach the performance of 302 103 MLUPS (Million Lattice Updates per Second).
Published in: 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)
Date of Conference: 21-23 June 2018
Date Added to IEEE Xplore: 16 August 2018
ISBN Information:
DOI: 10.23919/MIXDES.2018.8436913
Conference Location: Gdynia, Poland
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Contents

I. Introduction

ARUZ (Analizator Rzeczywistych Ukladow Zlozonych, Analyser of Real Complex Systems) is a massively parallel FPGA-based simulator located at Lodz Technopark. This machine has been designed for execution of a single algorithm (Dynamic Lattice Liquid-DLL [1]) in mind [2] [3]. Recently an implementation of the Lattice Boltzmann method [4] on ARUZ has been presented [5]. This paper presents an improvement to this implementation.

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