Improvement of Row Hammering Using Metal Nanoparticles in DRAM—A Simulation Study

In this letter, we investigate row hammering (RH) in recessed channel access transistor (RCAT)-DRAM cells. A novel technique is proposed to minimize the row hammer fail in DRAM cells by selective/local introduction of metal nanoparticles (MNPs) at the gate metal-oxide interface. Using TCAD simulations, we show that the introduction of MNPs with an optimized work function (WF) significantly reduces the storage node leakage of unaccessed DRAM cells (victim cells) due to the hammered access of neighboring DRAM cells (aggressor cells) sharing a common bit line. The proposed technique potentially eliminates row hammer fail in RCAT-DRAM cells at 2X and 1X nodes. The improvement in row hammer fail is due to the dual-energy valley induced between the neighboring DRAM cells by the introduction of MNPs. These valleys prevent diffusion of electrons from the aggressor cell to the victim cell, which improves row hammer fail. This letter shows that the introduction of MNPs is a promising technique to eliminate row hammer fail in DRAM cells.

I. Introduction

Interference among DRAM cells due to leakage through the isolation between neighboring word lines is one of the major reliability concerns at the 2X technology node [1], [2]. Frequent accessing of a row (aggressor row) introduces a parasitic coupling among the adjacent unaccessed rows (victim rows), which causes the rows to interact in an undesired way and results in bits flipping in the victim row [3], [4]. In the recent past, the row hammering (RH) phenomenon has been discussed in detail and researchers have proposed both architectural and fabrication techniques to minimize RH. The authors in [3] reported that toggling the aggressor row 139K times can introduce errors in victim rows and proposed an architectural solution to surmount these errors. The authors in [5] investigated the failure mechanism in DDR3 DRAM with different test parameters and replicated the failure mechanism with SPICE simulation using TCAD models. The authors in [5] reported the victim cell voltage degradation from 1V to 0V after only five hammers, which is not clearly understood. On the other hand, the authors in [3] and [6] reported that approximately 10⁵ hammered access of an aggressor row can introduce significant errors in victim rows. Based on the failure mechanism discussed in [5], the authors in [7] proposed a fabrication technique to minimize the fail bit count through implanting phosphorous with a 2X dose in the bit line (BL). However, increasing BL doping reduces the access transistor channel length.