Systematic analysis of ESD-induced soft-failures as a function of operating conditions

Electrostatic discharges (ESD) to parts of a system can lead to system-level soft-failures. These failures can depend on the activity of the system at the moment of discharge. This paper investigates ESD susceptibility as a function of different operating conditions such as software loading, clock frequency, and VDD voltage. Due to the large number of possible conditions, a commercial automated ESD scanner is modified and used to obtain ESD susceptibility maps for each operating condition. The core processor of a single-board computer is selected as the device under test. It is observed that the processor becomes more sensitive to ESD events as its software loading increases. The effect of VDD voltage and clock frequency on the sensitivity of the processor is also discussed. Moreover, the effect of increasing the power distribution network impedance and noise is investigated, partially leading to counterintuitive results.

I. Introduction

Electrostatic discharges (ESD) can couple into an integrated circuit (IC) via its pins and cause different types of system-level failures. ESD energy can also directly couple to the bond wires and cause a failure. Typical examples are loss of data, data corruption, program termination, system hang, system reset, latch-up, etc. These type of failures are known as soft-failures as the system recovers by power-cycling. Soft-failures can be grouped into two categories with respect to software loading conditions: those that are not affected by the core processor loading and those that have an increased likelihood to occur if the processor is highly active [1]. For instance, coupling to the reset circuitry or system clock will most likely lead to a system reset or hang up, independent of the loading condition. However, memory access disturbance will only lead to visible effects if the memory was active at the moment of the disturbance.