Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method

Reliability is one of the major concerns for ultralow power circuit designs. Markov random field (MRF) techniques have been applied to logic circuits to resist random noise when operating under ultralow supply voltage or sub-threshold voltage. Although conventional MRF networks can be easily mapped onto simple logic circuits, it becomes difficult when the circuits are large and complex. In this paper, we present a general coding-based partial MRF (CPMRF) method for multi-logic operations in one basic unit, which is referred to as a CPMRF pair. A CPMRF pair saves circuit area by sharing a common MRF network. It also inherits noise immunity from the MRF theory while obtaining noise immunity from the coding structure as a combination of robust “1s” and “0s.” The resulting architectures become more cost effective than conventional ones. To validate the performance of our proof-of-concept design, we fabricated a carry-lookahead adder implemented by the proposed CPMRF pairs using IBM 130-nm CMOS technology. Measurement results indicate that the CPMRF CLA can achieve high noise tolerance with 20% improvement while occupying 37.7% less area and reducing power consumption by 93% compared with the master-and-slave MRF CLA design.

I. Introduction

The continuous miniaturization of electronic components has enabled rapid growth of microelectronics over the past decades. One of the most important attributes of nanoscale devices is their low-power consumption. However, when the supply voltage is scaled down, the energy difference between logic states is comparable to the surrounding noise, rendering the resulting circuit vulnerable to operational uncertainty and logic failures [1]. These signal errors are dynamic in nature, occurring anywhere in the circuit, and are difficult to detect by regular testing methodologies [1]. Such errors are often referred to as “dynamic errors.” As the dimensions of devices scale down further into the nanometer realm, one of the major challenges we will need to confront is the increasing prevalence of dynamic errors in nanoscale logic circuits.