Dynamic Capacitance Model of a Pinned Photodiode in CMOS Image Sensors

The charge holding capacity of a pinned photodiode (PPD) in CMOS image sensors (CISs) is determined by the capacitance of the photodiode. A PPD with a higher full-well capacity (FWC) is desirable for a higher dynamic range and image contrast thereby improving the image quality. The dependence of FWC of a PPD on light intensity and integration time is reported in the literature. However, there is no generalized method to estimate the PPD capacitance. The reported models assume the PPD capacitance to be constant and independent of operating conditions. This paper presents an improved model to accurately estimate the dynamic behavior of the PPD capacitance at low and high light intensity levels and varying temperature in CISs. It is observed that the logarithmic increase in light intensity and integration time increases the photodiode capacitance linearly. The model shows good agreement with the simulated and measured values of photodiode capacitance.

I. Introduction

A CMOS image sensor (CIS) with a pinned photodiode (PPD) is used in many applications of electronic imaging. A PPD is known for its low noise, no image lag, high sensitivity, and wide dynamic range (DR) [1], [2]. All these characteristics are desired for a good quality image and are characterized by the full-well capacity (FWC) of the PPD. It is thus very important to understand the characteristics of the FWC of the photodiode. The FWC of a PPD is defined as the maximum amount of charges a photodiode can hold before saturating. However, the FWC of the pixel is determined by the minimum of charge handling capability of the PPD or the floating diffusion (FD) node for complete charge transfer, if not limited by readout signal chain [1].