Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG

Development of an industry leading 10nm CMOS process technology with the highest reported drive currents and cell densities involved numerous enabling innovations, judicious choice of design rules, novel features, and most importantly a relentless pursuit of performance-reliability co-optimization. This paper reports that Intel's 10nm technology achieved scaling benefit over its preceding 14nm generation at matched or better transistor reliability. An elaborate study of the challenges to scaling is presented, which once addressed, enabled meeting aggressive technology reliability targets.

I. Introduction

In order to achieve the industry leading transistor performance and layout density, Intel's 10nm technology leveraged both scaling of critical transistor features sizes from its preceding 14nm process generation, and introduction of new density enhancement features to reduce unused spaces within the standard cells [1], [2]. Such aggressive geometric scaling, however, lead not only to a formidable number of process integration challenges, but the process options also started to demonstrate complex multi-dimensional interactions among various transistor reliability mechanisms, requiring a careful consideration of their overall reliability impact [3]–[5].