A Highly Parallel Hardware Architecture of Table-Based CABAC Bit Rate Estimator in an HEVC Intra Encoder

This paper presents a highly parallel hardware architecture for rate estimation in a High Efficiency Video Coding intra encoder to increase the level of parallelism and reduce the computational time. The adopted rate estimation algorithm is fully compatible with the context-adaptive binary arithmetic coding (CABAC) bit rate estimation except ignoring a syntax element “split_cu_flag.” Design considerations, analysis, and circuit implementation are elaborated. This design has been verified with the HM-15.0 reference software. It achieves an average decrease of 0.005% and an average increase of 0.0092 dB in Bjøntegaard delta (BD)-rate and BD-peak signal-to-noise ratio, respectively. This proposed hardware architecture is implemented in Verilog and synthesized in FPGAs and ASICs. It supports resolutions up to 3840 × 2160 at 30 f/s. Compared with stateof-the-art hardware designs for rate estimation in the literature, the proposed architecture achieves substantial performance improvement in rate estimation accuracy and reliability, with the overhead of a relatively larger chip area and higher power consumption. To the best of our knowledge, this is the first highly parallel hardware architecture of table-based CABAC bit rate estimator, which is attractive in time-constrained and highperformance video coding applications.

I. Introduction

With the aim of enabling advanced video compression for emerging applications (e.g., ultra-high-definition (UHD) 4K/8K TV), a High Efficiency Video Coding (HEVC) has been established recently. Compared with H.264, HEVC keeps the same video quality and meanwhile boosts the compression efficiency by around 50% [1], [2]. HEVC has great potential to satisfy these emerging time-constrained, high-resolution video coding applications. To realize superior compression efficiency, new concepts and features have been introduced in HEVC intra encoder [3]. For example, coding tree unit (CTU) in HEVC replaces macroblock in H.264. A CTU size may vary from to . Each CTU contains one or more coding units (CUs), whose sizes are allowed from up to . According to a quad-tree structure, a CU may be split into four smaller CUs. A CU is associated with its prediction units (PUs) and transform units (TUs). A PU, whose size is from to , includes luma and chroma prediction information. Discrete sine transform (DST) and discrete cosine transform (DCT) are allowed in TUs to transform prediction errors. DST deals with luma prediction residuals in TUs, while other TUs are transformed by DCT. In addition to the CTU concept, intra prediction modes increase to 35, including planar, DC and 33 directional modes. This CU/PU/TU concept and 35 prediction modes enable larger design space exploration than H.264. Despite enhanced compression efficiency, the resultant computational complexity in HEVC intra encoder is tremendous [2]–[5].