I. Introduction
GaN-based electronic devices are excellent candidates for power applications due to the superior physical properties of GaN compared to Si, SiC and GaAs. Recently, GaN vertical devices have attracted increased attention, due to their advantages over GaN lateral devices for high-power switching: (a) higher breakdown voltage (BV) and current capability for a given chip size, (b) superior reliability gained by moving the peak electric field away from the surface into bulk devices, and (c) easier thermal management [1]. Vertical GaN transistors [2]–[6] and diodes [7]–[9] with excellent performance have been recently demonstrated on GaN substrates. However, the high cost and small diameter of GaN substrates is an important obstacle for the commercialization of GaN-on-GaN vertical power devices. GaN vertical devices on low-cost Si substrates are therefore highly desired, as they could allow for at least 50-to-100-fold lower wafer and epitaxy cost as well as the possibility of processing on 8-inch Si substrates [10]. However, the insulating buffer layers, which are typically needed to handle the lattice mismatch and thermal stress in GaN-on-Si wafers, make it challenging to realize the vertical current conduction in GaN-on-Si vertical power devices.