Abstract:
In this work, we demonstrate that the magnitude of flatband voltage (V/sub FB/) shift for ultrathin (<2 nm) silicon dioxide-silicon nitride (ON) gate stacks in MOSFET's d...Show MoreMetadata
Abstract:
In this work, we demonstrate that the magnitude of flatband voltage (V/sub FB/) shift for ultrathin (<2 nm) silicon dioxide-silicon nitride (ON) gate stacks in MOSFET's depends on the Fermi level position in the gate material. In addition, a fixed positive charge at the oxide-nitride interface was observed.
Published in: IEEE Electron Device Letters ( Volume: 21, Issue: 4, April 2000)
DOI: 10.1109/55.830971
Citations are not available for this document.
Cites in Patents (4)Patent Links Provided by 1790 Analytics
1.
Jang, Kyoung Chul, "Semiconductor device and method for forming the same"
Inventors:
Jang, Kyoung Chul
Abstract:
A semiconductor device includes a semiconductor substrate including a trench, a gate insulation film located over a bottom and sidewall of the trench, a first gate formed over the gate insulation film and in a lower portion of the trench, a second gate formed over the first gate and in an upper portion of the trench, a multi-layered structure provided between the gate insulation film and the second gate.
Assignee:
SK HYNIX INC
Filing Date:
24 September 2014
Grant Date:
23 February 2016
Patent Classes:
Current International Class:
H01L0296600000, H01L0297600000, H01L0294230000, H01L0297800000, H01L0291000000, H01L0295100000, H01L0213060000, H01L0210200000, H01L0271080000
2.
Chua, Thai Cheng; Czarnik, Cory; Olsen, Christopher Sean; Ahmed, Khaled Z.; Kraus, Philip Allan, "METHOD FOR FABRICATING A GATE DIELECTRIC OF A FIELD EFFECT TRANSISTOR"
Inventors:
Chua, Thai Cheng; Czarnik, Cory; Olsen, Christopher Sean; Ahmed, Khaled Z.; Kraus, Philip Allan
Abstract:
A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. Optionally, the gate dielectric layer may be nitridized prior to oxidizing the gate dielectric layer. In one embodiment, at least portions of the method are performed using processing reactors arranged on a cluster tool.
Assignee:
APPLIED MATERIALS INC
Filing Date:
20 October 2005
Grant Date:
15 February 2011
Patent Classes:
Current U.S. Class:
438287000, 257E21639, 257E21670, 438591000, 438772000, 438775000, 438908000
Current International Class:
H01L0213360
3.
Chua, Thai Cheng; Czarnik, Cory; Hegedus, Andreas G.; Olsen, Christopher Sean; Ahmed, Khaled Z.; Kraus, Philip Allan, "METHOD FOR FABRICATING A GATE DIELECTRIC OF A FIELD EFFECT TRANSISTOR"
Inventors:
Chua, Thai Cheng; Czarnik, Cory; Hegedus, Andreas G.; Olsen, Christopher Sean; Ahmed, Khaled Z.; Kraus, Philip Allan
Abstract:
A method for fabricating a gate dielectric of a field effect transistor is provided. In one embodiment, the method includes removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer, and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma. In another embodiment, the oxide layer on the gate dielectric layer is formed by forming a thermal oxide layer, i.e., depositing the oxide layer on the gate dielectric layer.
Assignee:
APPLIED MATERIALS INC
Filing Date:
05 May 2006
Grant Date:
01 June 2010
Patent Classes:
Current U.S. Class:
438197000, 257E21170, 257E21284, 257E21293, 257E21311, 257E21632, 438770000, 438775000
Current International Class:
H01L0213360, H01L0218234
4.
Matsushita, Daisuke; Muraoka, Koichi; Nakasaki, Yasushi; Kato, Koichi; Shimizu, Takashi, "SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME"
Inventors:
Matsushita, Daisuke; Muraoka, Koichi; Nakasaki, Yasushi; Kato, Koichi; Shimizu, Takashi
Abstract:
According to an aspect of the present invention, there is disclosed a semiconductor device comprising a semiconductor substrate, and a gate insulating film of a P-channel MOS transistor, formed on the semiconductor substrate. The gate insulating film has an oxide film (SiO 2 ), and a diffusion preventive film (BN) containing boron and nitrogen atoms.
Assignee:
KK TOSHIBA
Filing Date:
05 August 2005
Grant Date:
03 July 2007
Patent Classes:
Current U.S. Class:
257411000, 257410000, 257E21267, 257E21292, 257E29132, 257E29165, 257E29255, 438216000, 438261000, 438287000, 438591000
Current International Class:
H01L0299400
