Contents I. Introduction
High-mobility III-V materials such as InGaAs are being considered to replace strained Si in nFETs for future low power logic application [1]–[3]–. Besides this, III-V channel materials have been shown to be well-suited for 2D co-planar [4] or 3D monolithic integration with Si/SiGe FETs [5], [6], in a 3D circuit demonstration [7]. Multi-gate device architecture has become the preferred solution for advanced technology nodes. For aggressive scaling, fin dimension scaling is necessary in order to maintain electrostatic integrity [2], [8], [9]–. This requires highly optimized processes both for the fin and gate definition. While small fin sizes have already been demonstrated recently with a replacement metal gate flow [10], [11], these demonstrations have been limited to relatively larger . In this work, we combine small fin width and short gate length for an InGaAs-on-Insulator replacement metal gate FinFET on a Si substrate. It allows us to demonstrate a CMOS-compatible InGaAs n-FinFET suitable for both 2D and 3D monolithic integration with the highest reported performance to date on Si, at a gate length comparable to recent report on sub-7 nm node targets [12]. At nm, we show low subthreshold swing (SS), low drain-induced barrier lowering (DIBL) and a record of 249 at a fixed OFF-current of 100 and supply voltage V. We also investigate the contribution from short-channel effects and carrier generation/recombination on SS and using calibrated full 3D and simplified 2D TCAD simulations.
