A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC

A low-power 10-bit converter that can sample input frequencies above 100 MHz is presented. The converter consumes 55 mW when sampling at f/sub s/=40 MHz from a 3-V supply, which also includes a bandgap and a reference circuit (70 mW if including digital drivers with a 10-pF load). It exhibits higher than 9.5 effective number of bits for an input frequency at Nyquist (f/sub in/=f/sub s//2=20 MHz). The differential and integral nonlinearity of the converter are within /spl plusmn/0.3 and /spl plusmn/0.75 LSB, respectively, when sampling at 40 MHz, and improve to a 12-bit accuracy level for lower sampling rates. The overall performance is achieved using a pipelined architecture without a dedicated sample/hold amplifier circuit at the input. The converter is implemented in double-poly, triple-metal 0.35-/spl mu/m CMOS technology and occupies an area of 2.6 mm/sup 2/.