Abstract:
This letter proposes a fast and precise high-speed channel modeling and optimization technique based on machine learning algorithms. Resistance, inductance, conductance, ...Show MoreMetadata
Abstract:
This letter proposes a fast and precise high-speed channel modeling and optimization technique based on machine learning algorithms. Resistance, inductance, conductance, and capacitance (RLGC) matrices of a high-speed channel are precisely modeled by design-of-experiment method and artificial neural network. In addition, an optimal channel design, which achieves minimum channel loss and crosstalk, is investigated within short time by a genetic algorithm. The performance of the proposed technique is validated by simulations up to 20 GHz.
Published in: IEEE Transactions on Electromagnetic Compatibility ( Volume: 60, Issue: 6, December 2018)
Funding Agency:
References is not available for this document.
Contents Select All
1.
S. Ahn, A. W. Lu, W. Fan, L. L. Wai and J. Kim, "Effects of process variation on signal integrity for high speed differential signaling on package level", Proc. IEEE Electron. Packaging Technol. Conf., pp. 249-252, Dec. 2002.
2.
S. J. Park, B. Bae, J. Kim and M. Swaminathan, "Application of machine learning for optmization of 3-D integration circuits and systems", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 6, pp. 1856-1865, Jun. 2017.
3.
W. T. Beyene, "Application of artificial neural networks to statistical analysis and nonlinear modeling of high-speed interconnect system", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 1, pp. 166-176, Jan. 2007.
4.
F. Wang, V. Kumar, Devabhaktuni and Q. Zhang, "A hierarchical neural network approach to the development of a library of neural models for microwave design", IEEE Trans. Microw. Theory Techn., vol. 46, no. 12, pp. 2391-2403, Dec. 1998.
5.
P. M. Watson and K. C. Gupta, "Design and optimization of CPW circuits using EM-ANN models for CPW components", IEEE Trans. Microw. Theory Techn., vol. 45, no. 12, pp. 2515-2523, Dec. 1997.
6.
C. Chung et al., "A delay line circuit design for crosstalk minimiation using genetic algorithm", IEEE Trans. Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 3, pp. 578-583, Feb. 2008.
7.
Y. Zhang, J. Xu, Y. Wang, B. Sen, C. Sui and J. Fan, "Creating generic models for high-speed channels using the design of experiment method", Proc. DesignCon 2017, 2017.
8.
S. H. Hall and H. L. Heck, Advanced Signal Integrity for High-Speed Digital Designs, New York, NY, USA::Wiley, 2009.
