Abstract:
Polycrystalline silicon thin film transistors were fabricated using both self-aligned and non-self-aligned structures on 0.2 mm steel foil substrates coated with 0.5 /spl...Show MoreMetadata
Abstract:
Polycrystalline silicon thin film transistors were fabricated using both self-aligned and non-self-aligned structures on 0.2 mm steel foil substrates coated with 0.5 /spl mu/m SiO/sub 2/. The polycrystalline silicon was formed by furnace crystallization of PECVD hydrogenated amorphous silicon films at temperatures from 600 to 950/spl deg/C. The corresponding annealing times at high temperature can be as short as 20 seconds. No evidence is found for transistor contamination by the steel with drain current on/off ratio of /spl ges/10/sup 5/ in all cases. The short crystallization times achievable on steel substrates provide a considerable advantage over glass substrates, which require crystallization times of /spl ges/6 hours because of their strain temperatures of /spl sim/600/spl deg/C. Our results lay the groundwork for polycrystalline silicon transistor roll-to-roll technology on continuous web.
Date of Conference: 05-08 December 1999
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-5410-9
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