PCB PDN Prelayout Library for Top-Layer Inductance and the Equivalent Model for Decoupling Capacitors

The power distribution network (PDN) of a high-speed printed circuit board requires a high-performance power supply. The total equivalent inductance above the top ground plane is an important part of PDN design and is regarded as Labove. In this paper, an inductance library for different structures of capacitor connections and capacitor sizes has been built, which is essential for PDN design. computer simulation technology (CST) and partial element equivalent circuit method are applied to obtain the shorted pattern design curves at various design data. The shorted pattern design curve means the total equivalent inductance varies with the distance between pad and ground plane. In addition, an approximate shorted model is established for a decoupling capacitor-mounted model, which will be convenient for us to get the inductance of Labove. In this paper, the design curve provides an intuitive guideline in designing PDN and facilitates the industry to choose what they want with consideration of the inductance, space, via numbers, etc.

I. Introduction

POWER  integrity is important for high-speed printed circuit boards (PCBs) in the field of electromagnetic compatibility [1]. It considers whether the desired voltage and current have met the design requirements from sources to destinations. Reduction in voltage across the power supply terminals of the IC slows down the transistor or prevents the transistors from switching states; whereas, increases in voltage across the power supply terminals of the IC creates reliability problems. The impedance looking from the voltage regulator module (VRM) to IC part should meet the target impedance to ensure the dc ripple is not too large to effect the switching of the transistors. Therefore, it is essential to design a power distribution network (PDN) to meet the target impedance.