I. Introduction
In last years, the progressive reduction of the nominal supply voltage of integrated digital circuits, and the growing importance of energy harvesting, have motivated the development of low voltage analog cells. In CMOS circuits, the main problem comes from the minimum gate-source voltage required to drive the MOS devices. To solve this problem, one possible solution is opting for non-conventional architectures that uses bulk-driven MOSFETs [1], but this approach, due to the smaller gm/ID ratio, is far less efficient in terms of noise (or bandwidth) vs. current consumption tradeoff. On the other hand, it is possible to maintain the advantages of traditional gate-driven topologies, making them compliant with low supply voltage by pushing the MOSFETs in deep subthreshold region. However, many well-established topologies are not optimized in this respect, since they involve piling up of several gate-source voltages between the power rails. Then, selection of the best topologies or, possibly, the development of newer ones, is a key factor in the design of low voltage analog circuits.