A compact sub-1V class AB operational amplifier for low-voltage switched-capacitor circuits | IEEE Conference Publication | IEEE Xplore

A compact sub-1V class AB operational amplifier for low-voltage switched-capacitor circuits


Abstract:

A compact sub-1V class-AB operational amplifier to be used as a building block for low-voltage switched-capacitor architectures is presented. The proposed amplifier works...Show More

Abstract:

A compact sub-1V class-AB operational amplifier to be used as a building block for low-voltage switched-capacitor architectures is presented. The proposed amplifier works properly with supply voltages in the range 0.9 V-1.4 V, providing a gain-bandwidth product of 8 MHz, and a maximum output short-circuit current of 1 mA with 120 μA quiescent supply current. The performances of the operational amplifier are demonstrated by means of electrical simulations performed on a prototype designed with the UMC 0.18 μm / 3.3 V process. The total area of the cell, estimated from a preliminary layout, is 75×105 μm2.
Date of Conference: 04-06 September 2017
Date Added to IEEE Xplore: 02 November 2017
ISBN Information:
Electronic ISSN: 2474-9672
Conference Location: Catania, Italy

I. Introduction

In last years, the progressive reduction of the nominal supply voltage of integrated digital circuits, and the growing importance of energy harvesting, have motivated the development of low voltage analog cells. In CMOS circuits, the main problem comes from the minimum gate-source voltage required to drive the MOS devices. To solve this problem, one possible solution is opting for non-conventional architectures that uses bulk-driven MOSFETs [1], but this approach, due to the smaller gm/ID ratio, is far less efficient in terms of noise (or bandwidth) vs. current consumption tradeoff. On the other hand, it is possible to maintain the advantages of traditional gate-driven topologies, making them compliant with low supply voltage by pushing the MOSFETs in deep subthreshold region. However, many well-established topologies are not optimized in this respect, since they involve piling up of several gate-source voltages between the power rails. Then, selection of the best topologies or, possibly, the development of newer ones, is a key factor in the design of low voltage analog circuits.

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References

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