DFT-based analysis of the origin of traps at the InAs/Si (111) interface

Trap-assisted tunneling is known to detrimentally affect the performance of TFETs. To find the origin of traps at the InAs/Si interface, Density Functional Theory (DFT) based modeling of the interface is performed using the DFT tool CP2K. Geometrically optimized atomic positions at the InAs/Si interface obtained by using structural minimization are in qualitative agreement with TEM images reported in the literature. Electronic structure calculations using the optimized atomic structure reveal highly localized trap states at the InAs/Si interface. The trap states originate from unsaturated atomic orbitals on As atoms and are primarily localized at As atoms.

I. Introduction

Tunnel Field Effect Transistors (TFETs) are considered as viable alternatives for MOSFETs in low-power electronic applications. Previous studies on InAs/Si hetero-junction TFETs have shown that traps at the InAs/Si interface degrade their performance and inhibit a sub-thermal slope [1]. The investigation into origin and nature of such interface traps using ab-initio atomistic modeling would be a useful first step in mitigating their detrimental impact.