I. Introduction
Today's high speed digital electronics operate at clock frequencies as high as 5.5GHz, which require a power distribution network (PDN) that can maintain a constant voltage at several higher harmonics of this clock frequency. This requires the parallel combinations of printed circuit board (PCB) decoupling capacitors, power plane capacitance, on package capacitors and on-die decoupling [1] [2]. The limiting factor for the performance of these components is the parasitic inductances created by the paths that the current has to propagate to get to the load which are the switching transistors on the integrated circuits (IC).