I. Introduction
The concept of a transfer function model for digital circuits is devised wherein the input stimulus and the output response are represented by an element in a finite-dimensioned Hilbert vector space. This work describes the use of our past results to implement and evaluate a prototype simulation tool. The prototype parses a structural netlist in Verilog and constructs the transfer matrix for the netlist in the form of a BDD. Constructing the transfer function of a structural circuit description can be accomplished by partitioning the netlist into a serial cascade of parallel stages, constructing the transfer matrices of each stage through a tensor matrix multiplication, and combining the stages using direct matrix multiplication [1]. The advantage of our simulation approach is that it supports symbolic simulation wherein any of the inputs, or subsets of the inputs can be assigned both binary values simultaneously. In one extreme, all possible input values can be symbolically simulated with one vector-matrix computation. In the other extreme, a single input assignment can be simulated with one vector-matrix product.