1. Introduction
3D NAND Flash Memory is commonly believed to have high potential to gradually replace the conventional 2D NAND Flash Memory in the next few years. One challenge of 3D NAND is the select transistor leakage because of poly-Si based transistor [1]. Leakage current of drain select transistor in the string has great impact on self-boosting performance which is critical in program disturbance suppression in NAND Flash Memory [2]. In 2D planer NAND Flash Memory, Drain select transistor (DSL) with single crystalline silicon channel can be easily cut-off because of low subthreshold swing [1]. In addition, the transistor can be fabricated with a long channel conveniently in process. For DSL of a string in 3D NAND Memory, although a cylindrical structure with stronger gate controllability is usually used, leakage of DSL is still too large for a good self-boosting performance due to the use of polysilicon channel [3].
(a) Drain select transistor in vertical channel 3D NAND flash memory, dual transistors proposed as DSL in 3D NAND flash memory. (b)Schematic of cylindrical dual cylindrical transistors and corresponding bias condition applied in this work.