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String select transistor leakage suppression by threshold voltage modulation in 3D NAND Flash Memory | IEEE Conference Publication | IEEE Xplore

String select transistor leakage suppression by threshold voltage modulation in 3D NAND Flash Memory


Abstract:

Single drain select transistor (DSL) in 3D Flash memory may exhibit higher leakage as compared with DSL in 2D NAND, because of worse subthreshold swing characteristics du...Show More

Abstract:

Single drain select transistor (DSL) in 3D Flash memory may exhibit higher leakage as compared with DSL in 2D NAND, because of worse subthreshold swing characteristics due to poly-Si channel. Select transistor leakage suppression is essential in 3D NAND Flash Memory, in consideration of boosting potential and program disturbance. Compared to single Si drain select transistor in 2D planner Flash Memory, a novel dual cylindrical thin film transistor is proposed as drain select device to suppress leakage for good boosting performance in 3D NAND flash. And a novel measurement approach is also proposed to quantify leakage of drain select transistor in program inhibit case. The effect of Vth modulation on leakage is evaluated with this new DSL approach in this work. Single poly-Si cylindrical transistors demonstrated to be not applicable in 3D NAND because of high leakage. And the optimized Vth modulation pattern of dual transistors, with lower T1 Vth and higher T2 Vth has been found for good leakage suppression, which is beneficial for self-boosting performance of 3D NAND cell string.
Date of Conference: 25-28 October 2016
Date Added to IEEE Xplore: 03 August 2017
ISBN Information:
Conference Location: Hangzhou, China

1. Introduction

3D NAND Flash Memory is commonly believed to have high potential to gradually replace the conventional 2D NAND Flash Memory in the next few years. One challenge of 3D NAND is the select transistor leakage because of poly-Si based transistor [1]. Leakage current of drain select transistor in the string has great impact on self-boosting performance which is critical in program disturbance suppression in NAND Flash Memory [2]. In 2D planer NAND Flash Memory, Drain select transistor (DSL) with single crystalline silicon channel can be easily cut-off because of low subthreshold swing [1]. In addition, the transistor can be fabricated with a long channel conveniently in process. For DSL of a string in 3D NAND Memory, although a cylindrical structure with stronger gate controllability is usually used, leakage of DSL is still too large for a good self-boosting performance due to the use of polysilicon channel [3].

(a) Drain select transistor in vertical channel 3D NAND flash memory, dual transistors proposed as DSL in 3D NAND flash memory. (b)Schematic of cylindrical dual cylindrical transistors and corresponding bias condition applied in this work.

References

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