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Simulation on threshold voltage of L-shaped bottom select transistor in 3D NAND flash memory | IEEE Conference Publication | IEEE Xplore

Simulation on threshold voltage of L-shaped bottom select transistor in 3D NAND flash memory


Abstract:

A comprehensive simulation analysis method is proposed to improve the bottom select gate (BSG) transistor's Vth distribution by adopting under-channel implant in this wor...Show More

Abstract:

A comprehensive simulation analysis method is proposed to improve the bottom select gate (BSG) transistor's Vth distribution by adopting under-channel implant in this work. L-shaped bottom select transistor is used in TCAT 3D NAND array. Bottom select gate (BSG) Vth may exhibit broad distribution, due to various lateral distances between cell string and common source, which is an intrinsic challenge for TCAT-type 3D NAND flash array. In this work, an under channel implant scheme is proposed for BSG Vth distribution optimization. Simulation result shows that, with optimized implant dose approach, BSG Vth shows less sensitivity to string-common source distance, which is beneficial for cell characteristics distribution control in high density 3D NAND array. All these simulation results contribute to provide a guideline for boosting efficiency optimization in high density three dimensional (3D) NAND flash memory operation.
Date of Conference: 25-28 October 2016
Date Added to IEEE Xplore: 03 August 2017
ISBN Information:
Conference Location: Hangzhou, China

Introduction

To meet the storage requirement of big data, three dimensional (3D) NAND flash memory becomes the main trend of flash memory technology development. Recently, 3D NAND flash memory was developed and some advanced technology such as BiCS [1] and TCAT [2], has been proposed and demonstrated. Especially TCAT 3D NAND already started mass production. Increasing the number of strings in one block is effective approach to improve the storage density and reduce bit cost. More and more strings are integrated in one block. One string which is gate all around (GAA) structure consists of bottom select gate (BSG) transistor, memory cell and top select gate (TSG) transistor, as shown in Figure 1 and Figure 2. However, 3D memory array has inherent BSG distribution issue, due to string distribution in one block. Since the distance from each string to common source line (CSL) is different, BSG Vth has peak distribution with broad distribution, which leads to boosting potential distribution and will degrade boosting efficiency of each inhibit string at program operation. Moreover, a lower BSG Vth leads to a big leakage current in a inhibit string at program operation, while a higher BSG Vth induces a small channel current at read operation and leads to read error due to insufficient read sensing margin.

References

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