Introduction
To meet the storage requirement of big data, three dimensional (3D) NAND flash memory becomes the main trend of flash memory technology development. Recently, 3D NAND flash memory was developed and some advanced technology such as BiCS [1] and TCAT [2], has been proposed and demonstrated. Especially TCAT 3D NAND already started mass production. Increasing the number of strings in one block is effective approach to improve the storage density and reduce bit cost. More and more strings are integrated in one block. One string which is gate all around (GAA) structure consists of bottom select gate (BSG) transistor, memory cell and top select gate (TSG) transistor, as shown in Figure 1 and Figure 2. However, 3D memory array has inherent BSG distribution issue, due to string distribution in one block. Since the distance from each string to common source line (CSL) is different, BSG Vth has peak distribution with broad distribution, which leads to boosting potential distribution and will degrade boosting efficiency of each inhibit string at program operation. Moreover, a lower BSG Vth leads to a big leakage current in a inhibit string at program operation, while a higher BSG Vth induces a small channel current at read operation and leads to read error due to insufficient read sensing margin.