Contents I. Introduction
J.P.Colinge et. al. [1] proposed and demonstrated a new device structure, Junctionless Field Effect Transistor (JLFET) with constant heavy doping concentration in the source, channel and drain. The bulk conduction current flows in JLFET instead of surface conduction as in inversion mode MOSFET [2]. A large work function difference between gate material and channel semiconductor is required to make the channel fully depleted in Off state and appropriate gate voltage is required to make the channel partially depleted or neutral in On state of the device [3]–[4]. The JLFET shows superiority over junction based transistors in terms of easier fabrication, reduced short channel effects, higher scalability and less sensitive to thermal budget [1]–[6]. Apart from this, JLFETs show an interesting temperature behavior which reflects the effect of mobility variation with temperature in semiconductor devices due to different scattering phenomenon taking place. In junctionless FETs, the scattering is very less effective due to the bulk conduction mechanism which moderately degrades the mobility. This slight reduction in mobility cannot considerably reduce the drain current. Thus, Lee et. al. [7] have reported the temperature dependent electrical characteristics of Junctionless FETs and show that the junctionless FETs have larger threshold voltage variation than inversion and accumulation mode MOSFETs. They also find that no “zero temperature coefficient” (ZTC) point is evident in junctionless devices from 30C to 200C. Further, Han et al. [8] reported Temperature-dependent characteristics of junctionless bulk transistor by using 3D thermodynamic quantum-corrected device simulation and pointed out very important fact about ZTC point which exists above 200K but it does not exist at low temperatures. X.Li et. al. [9] demonstrated low temperature electron mobility in JLFET and they found that the minimum electron mobility at a critical low temperature is due to interplay of thermal activation and impurity scattering. M.de Souza et. al.[10] presented electrical properties of Junctionless FETs under cryogenic operation. They demonstrated that drain current decreases and maximum transconductance increase when temperature is lowered. Doria et. al.[11] demonstrated the analog performance metrics in the cryogenic temperature range of 100K to 473K. They demonstrated that the maximum transconductance shows parabolic relation with temperature and is insensitive to temperature. Further, Baruah and Paily [12] presented the effects of high-temperature on digital and analog performance parameters of short channel n-type symmetric DG-JLFET in the form of on-state and off-state current, subthreshold swing, intrinsic gain, cut-off frequency and gate capacitance by comparing it with conventional DGMOS. In general, the diffusion and ion implantation results in a Gaussian distributed doping profile which is possibly the most general doping profile from which different doping profiles can be derived by varying the straggle parameters of Gaussian function. In view of above, Gaussian doping profile provides more accurate results and makes the analysis more reliable. Recently, Mondal et. al. [13] has reported simulation based study of JLFET in silicon on insulator (SOI) with vertical Gaussian doping profile in the channel to show higher Ion/Ioff current ratio and improved leakage current than uniform doping profile in the channel of same device structure. They also reported the effect of non-uniform doping in the channel with 3D quantum simulation and showed the better short channel effects and higher threshold voltage [14].
