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A Thru-Halfthru-Short De-Embedding Method for Millimeter-Wave On-Wafer HBT Characterization | IEEE Journals & Magazine | IEEE Xplore

A Thru-Halfthru-Short De-Embedding Method for Millimeter-Wave On-Wafer HBT Characterization


Abstract:

In this letter, a cascade-based de-embedding method with thru-halfthru-short structures is presented for millimeter-wave on-wafer device characterization. Distributed eff...Show More

Abstract:

In this letter, a cascade-based de-embedding method with thru-halfthru-short structures is presented for millimeter-wave on-wafer device characterization. Distributed effects of interconnect, discontinuity between pad and interconnect, and transistor-access-via-holes are all well considered using only three dummy structures, and forward coupling is also investigated. By providing both extracted junction capacitors and S-parameter results of 0.5-μm InP DHBT transistor using proposed and existing de-embedding methods up to 220 GHz, better high frequency performance and particularly 21° improvement in phase accuracy for S11 as well as 12° for S21 at 220 GHz are obtained compared with the state-of-the-art cascade-based method.
Published in: IEEE Electron Device Letters ( Volume: 38, Issue: 6, June 2017)
Page(s): 720 - 723
Date of Publication: 12 April 2017

ISSN Information:


I. Introduction

For millimeter-wave (mm-wave) device modeling and integrated circuit designing, accurate characterization of transistor up to high mm-wave range has been significant. In order to eliminate the parasitic effects arising from probe pads and interconnects, several de-embedding methods based on lumped equivalent circuits [1]–[3] have been proposed in the past decades. They model the peripheral parasitics as lumped elements in series and parallel, and then subtract them by means of Z- and Y-parameter calculations. As the operation frequency increases over 40 GHz, distributed effects become prominent and the lumped-based methods, which model the interconnect as an impedance in series, are no longer suitable. Recently, many cascade-based de-embedding techniques were developed to improve de-embedding accuracy by taking the distributed effects into consideration. In [4], a pad-open-thru-short (POTS) method is presented, the interconnect is regarded as a 2-port network and then directly subtracted by ABCD matrix calculation. In addition, a scalable de-embedding approach solves the distributed effect by regarding the interconnect as a transmission line [5], [6], and another unique thru LLR structure is proposed to calculate the ABCD matrix of input network directly [7]. Although the parasitic effects of probe pads, transmission line, dangling leg, and forward coupling are well considered in these methods, the reference planes are just shifted from the center of pads (plane 1) to the device edge in the top metal layer (plane 3) as illustrated in Fig. 1, and the parasitics of transistor-access via-holes from the top metal layer to device are residual. Only in [8], the via-holes are mentioned. However, the unique thru structure with via-holes lead to an over-estimating of coupling effects between input and output network, and the ABCD matrix of interconnect line with via-holes is calculated based on a lumped-assumption of two elements without considering the distributed effects of interconnect lines.

Cross-section of the device under test structure with reference planes of de-embedding.

References

References is not available for this document.