Performance Evaluation of Network-on-Chip-Based H.264 Video Decoders via Full System Simulation

We present a full system simulation framework for a network-on-chip (NoC)-based H.264 video decoder. By combining both the communication, i.e., the NoC and the processing, i.e., H.264 modules, components into the same simulation framework, we present for the first time the capability of simulating NoCs exercised with truly real traffic. Such a simulator can be utilized to evaluate performance metrics of systems-on-chip where the communication is done via NoCs, which are predicted to be the future communication paradigm of such systems. Because the NoC is exercised with real traffic instead of synthetic traffic such evaluations and optimizations can be more accurate and can lead to better design solutions.

I. Introduction

Networks-on-Chip (NoCs) represent a new communication paradigm for integrated circuits with increasingly large number of cores, such as chip multiprocessors (CMPs) and multiprocessor systems-on-chip (MPSoC). The NoC concept replaces design-specific global on-chip wires with a generic on-chip interconnection network implemented by specialized routers that connect processing elements (PEs)—such as processors, application-specified integrated circuits, field-programmable gate arrays, memories, etc.—to the network and facilitate communications or links between them. The benefits of the NoC-based SoC design approach include scalability, predictability, and higher bandwidth to support concurrent communications [1].