Enhancing the Bandwidth of Low-Dropout Regulators Using Power Transmission Lines for High-Speed I/Os

Power supply rejection peaking in low-dropout (LDO) voltage regulators can lead to reduced bandwidth and efficiency. This paper presents a new design method by combining power transmission lines (PTLs) with LDOs for enhancing its bandwidth and efficiency. This approach is applicable for LDOs regulating high-speed I/O drivers. The PTL combined with decoupling capacitors on the package or board is used to mitigate the power supply noise (PSN). This methodology is demonstrated using printed circuit board test vehicles with off-the-shelf components. Compared to conventional approaches, the PTL solution showed an ~80% lower PSN.

I. Introduction

Modern computer systems often include many voltage supplies. These are generated using dc–dc converters where buck converters are used to step-down the voltage from a main dc supply. Depending on the voltage conversion ratio, buck converters have a power efficiency in the range of 70%–90% [1]–[4]. The buck converters are also referred to as voltage regulator modules (VRMs). To improve both power efficiency and voltage regulation, the recent trend is to move toward fully integrated voltage regulators (FIVR) to supply both the core and I/O circuits for system-on-chip (SoC) applications [5]–[7]. One implementation of FIVR is to integrate the buck converter with SoC as a two-chip solution on a package with passives such as inductors and capacitors either surface mounted or embedded in the package [8].