Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride and nitrided oxide dielectrics | IEEE Journals & Magazine | IEEE Xplore

Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride and nitrided oxide dielectrics


Abstract:

Ultrathin oxynitride using plasma assisted deposition was evaluated against thermal oxide and nitrided thermal oxide as an alternative direct tunneling gate dielectric to...Show More

Abstract:

Ultrathin oxynitride using plasma assisted deposition was evaluated against thermal oxide and nitrided thermal oxide as an alternative direct tunneling gate dielectric to thermal oxide in the 2.5-nm regime. The oxynitride showed an enhanced high field effective mobility relative to the thermal oxide although the low field mobility was slightly depressed. The N/sub 2/O nitrided oxide showed an enhanced high field effective mobility with no degradation in low field mobility. The interface state density of the oxynitride was equivalent to that of the thermal and nitrided thermal oxides; a very welcome observation for this deposition chemistry and anneal conditions.
Published in: IEEE Electron Device Letters ( Volume: 20, Issue: 9, September 1999)
Page(s): 442 - 444
Date of Publication: 30 September 1999

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Cites in Papers - |

Cites in Papers - IEEE (4)

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1.
Kow-Ming Chang, Wen-Chih Yang, Bing-Fang Hung, "High-performance RSD poly-Si TFTs with a new ONO gate dielectric", IEEE Transactions on Electron Devices, vol.51, no.6, pp.995-1001, 2004.
2.
Kow-Ming Chang, Wen-Chih Yang, Chiu-Pao Tsai, "Performance and reliability of low-temperature polysilicon TFT with a novel stack gate dielectric and stack optimization using PECVD nitrous oxide plasma", IEEE Transactions on Electron Devices, vol.51, no.1, pp.63-67, 2004.
3.
Kow-Ming Chang, Wen-Chih Yang, Chiu-Pao Tsai, "Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric", IEEE Electron Device Letters, vol.24, no.8, pp.512-514, 2003.
4.
W.K. Henson, N. Yang, S. Kubicek, E.M. Vogel, J.J. Wortman, K. De Meyer, A. Naem, "Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime", IEEE Transactions on Electron Devices, vol.47, no.7, pp.1393-1400, 2000.

Cites in Papers - Other Publishers (9)

1.
Masafumi Kunii, "Hot-Carrier Immunity of Polycrystalline Silicon Thin Film Transistors Using Silicon Oxynitride Gate Dielectric Formed with Plasma-Enhanced Chemical Vapor Deposition", Japanese Journal of Applied Physics, vol.48, no.11, pp.116507, 2009.
2.
S. J. Chang, C. K. Wang, Y. K. Su, C. S. Chang, T. K. Lin, T. K. Ko, H. L. Liu, "GaN MIS Capacitors with Photo-CVD SiN[sub x]O[sub y] Insulating Layers", Journal of The Electrochemical Society, vol.152, no.6, pp.G423, 2005.
3.
Ching-Wei Chen, Chao-Hsin Chien, Tsu-Hsiu Perng, Chun-Yen Chang, "Hot-Electron-Induced Electron Trapping in 0.13 μm nMOSFETs with Ultrathin (EOT=1.6 nm) Nitrided Gate Oxide", Electrochemical and Solid-State Letters, vol.8, no.8, pp.G187, 2005.
4.
Kow-Ming Chang, Wen-Chih Yang, Bing-Fang Hung, "Low-Temperature Poly-Si Thin-Film Transistor with a N[sub 2]O-Plasma ONO Multilayer Gate Dielectric", Electrochemical and Solid-State Letters, vol.7, no.7, pp.G148, 2004.
5.
B S Sahu, A Kapoor, P Srivastava, O P Agnihotri, S M Shivaprasad, "Study of thermally grown and photo-CVD deposited silicon oxide–silicon nitride stack layers", Semiconductor Science and Technology, vol.18, no.7, pp.670, 2003.
6.
Rajnish K. Sharma, Ashok Kumar, John M. Anthony, "Advances in high-k dielectric gate materials for future ULSI devices", JOM, vol.53, no.6, pp.53, 2001.
7.
S.K. Ray, S. Maikap, S.K. Samanta, S.K. Banerjee, C.K. Maiti, "Charge trapping characteristics of ultrathin oxynitrides on Si/Si1−x−yGexCy/Si heterolayers", Solid-State Electronics, vol.45, no.11, pp.1951, 2001.
8.
C.H. Chen, Y.K. Fang, C.W. Yang, S.F. Ting, Y.S. Tsair, M.F. Wang, S.C. Chen, C.H. Yu, M.S. Liang, "Effects of post-deposition treatments on ultrathin nitride/oxide gate stack prepared by RTCVD for ULSI devices", Solid-State Electronics, vol.45, no.3, pp.461, 2001.
9.
J Suñé, M Nafría, E Miranda, X Oriols, R Rodríguez, X Aymerich, "Failure physics of ultra-thin SiO2gate oxides near their scaling limit", Semiconductor Science and Technology, vol.15, no.5, pp.445, 2000.
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