An Eight-Element 2–16-GHz Programmable Phased Array Receiver With One, Two, or Four Simultaneous Beams in SiGe BiCMOS

This paper presents an eight-element 2-16-GHz programmable phased array (PPA) receiver in a 0.13-μm SiGe BiCMOS with the reconfigurable number of beams and with the digital beamforming (DBF) capabilities. The eight-element chip can be configured for one, two, or four simultaneous beams or as an element-level DBF receiver. This is achieved using reconfigurable input switching and output combining networks with wideband active switches and combiners. The phased array channel results in a 5-b performance at 3-14 GHz (rms error <;5°) and a 4-b performance at 2-16 GHz (rms error <;8.5°). Each channel also contains a 3-b variable gain amplifier with 8-dB gain control at 2-16 GHz. The chip results in an 8-12-dB gain at 2-16 GHz (depending on the PPA mode), a noise figure (NF) of 12 dB, and an input P1 dB of -20 dBm per channel when all channels are activated. The chip consumes 250 mW per channel, which is competitive knowing its bandwidth and linearity. The DBF function also results in a wideband response with a gain and an NF of 15-16 and 12-13 dB, respectively, and high linearity (input P1 dB = -16 dBm) at 2-16 GHz. The programmable phased array receiver allows a single chip to be used over S-, C-, X-, and Ku-bands for a variety of applications such as satellite communications and point-to-point links. This results in faster and lower-cost phased array development since the same chip and its field-programmable gate array control can be reused from system to system, but with different antenna and grid spacing. The PPA removes the need to develop a different chip for every application and allows the development of phased arrays at commercial scales.

I. Introduction

SiGe and CMOS technologies are now extensively employed for RF and digital beamforming (DBF) phased array systems and allows a high level of integration between the analog RF and digital control functions [1], [2], a large number of channels (4–16 channels) on the same chip [3]–[6], and in some cases two to four simultaneous beams synthesized on-chip using RF combining techniques [1], [4], [7], [8]. These chips are individually designed and fabricated for every specific frequency and number of beams, which results in a substantial design effort for a particular application [9]–[14]. Since the nonrecurrent engineering design and mask cost of these chips is very high, the final chip cost is high for medium-volume applications and this limits the use of SiGe and CMOS chips for a variety of medium to low-volume systems. A high demand for a single chip can only exist when the SiGe or CMOS design satisfies multiple applications using the same chip. Example of such multipurpose chips are 2–8 or 2–16-GHz phased array receiver chips with multiple channels and single-beam operation, or 5–13-GHz -, -, and -band satellite communication chips capable of synthesizing multiple simultaneous beams (1, 2, or 4 beams) [4], [15]. Fig. 1.

Reconfigurable phased array receiver chip for multiple applications at different frequencies. (a) Single beam with chip connected to eight antennas. (b) Dual beams with chip connected to four antennas. (c) Four beams. (d) DBF with chip connected to two antennas. The antennas are always spaced 0.5– for a phased array with wide scan angle capabilities.