Distributed neural network: Dynamic learning via backpropagation with hardware neurons using arduino chips | IEEE Conference Publication | IEEE Xplore

Distributed neural network: Dynamic learning via backpropagation with hardware neurons using arduino chips


Abstract:

In this paper we present an implementation of and a proposed algorithm for an easily expandable hardware Artificial Neural Network (ANN) capable of learning using inexpen...Show More

Abstract:

In this paper we present an implementation of and a proposed algorithm for an easily expandable hardware Artificial Neural Network (ANN) capable of learning using inexpensive, off-the-shelf microprocessors. While significant work has been done in hardware ANN implementations, this research offers a unique, general use, unspecialized, and inexpensive model with a flexible architecture representation. Using Arduino Pro Mini microprocessors and a flexible data communication framework that makes use of the built-in circuit bus called the Inter-Integrated Circuit, this implementation involves the programming of one neuron per microchip. This one to one ratio allows for the computational parallelism inherent in neural networks and provides for the flexibility of building various ANN architectures. The prototype that was developed consists of an input layer element microchip, two hidden layer neuron microchips, and an output layer neuron microchip. Learning happens completely on hardware via backpropagation without a data connection to a computer. Tests showed that the prototype can learn the logical operations OR, AND, XOR, and XNOR, and that the system can accommodate dynamic changes in learning between logical operations.
Date of Conference: 24-29 July 2016
Date Added to IEEE Xplore: 03 November 2016
ISBN Information:
Electronic ISSN: 2161-4407
Conference Location: Vancouver, BC, Canada

I. Introduction

An Artificial Neural Network (ANN) models a biological neural network, which can have billions of neurons with trillions of interconnections. Most ANN s are implemented solely in software simulations, and those implemented in hardware usually have the whole ANN loaded on one chip. This research takes a step towards a new ANN implemented by connecting a number of microchips such that each microchip represents a single neuron. While the commercial market does have a host of hardware ANN s, no general use, unspecialized, and inexpensive model exists such that it has a clear one chip to one neuron representation. Generally, extra modules and processing parts are added to have the chip function as a single neuron and more commonly multiple neurons are implemented on one chip. Under-the-hood, these representations also generally require a good grasp of electrical engineering to fully understand how the inputs and outputs are mapped as they use voltage, current, and similar elements to model data. In order to manipulate these elements, specialized and expensive parts are often needed. Moreover, many of the architectures are built for specific tasks, and they are not easily incorporated into bigger systems, and even fewer have learning capabilities. This paper presents a more accessible approach for creating general hardware ANN s capable of learning.

Contact IEEE to Subscribe

References

References is not available for this document.