A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic

Low power and robust circuitry are permanent hotspots in VLSI design. Adiabatic logic is one of potential breakthroughs for these goals. Especially, designing reliable clock tree is very significant for adiabatic logic due to four-phase clocked power required for pipelined data transmission in adiabatic system. In this paper, we present analysis of charging speed and clock types that influence power dissipation in adiabatic logic and comparison of current mainstream clock generators suitable for adiabatic system. Based on the characteristics of current designs, using TSMC 180nm fabrication process, we propose a novel mixed clock generator, including four-phase source, switch controller and clock MUX to build a robust clock using only one reference clock. The test shows that below 600MHz, the proposed design has negligible signal attenuation with low power dissipation. We have also compared our work and current designs in device cost, and suitable work frequency based on circuit structure.

I. Introduction

Adiabatic logic is one of effective methods of low power VLSI design [1]. The essence of adiabatic logic includes lowering charging speed and clocked power supply, both of which can reduce power dissipation to a large degree. Lots of work [2]–[5] proposed the optimization of adiabatic circuitry, and reported the breakthrough in the view of system using adiabatic logic [6], [7]. Besides, how to drive adiabatic logic using clocked power decides the performance of following system. Currently mainstream adiabatic systems need four-phase clocked power to achieve energy recovery and correct data flow, and most of well used designs are built by integrating passive devices to clock block [8]–[10], which occupies more chip area. This paper presents a low cost clocked power driving adiabatic system without passive devices. The main work is described as follows: 1) We mathematically analyzed the slow charge and three types of clocked powers used for adiabatic logic in the view of power dissipation; and 2) Based on the mainstream designs of clocked power, we proposed a novel mixed clock generator without passive devices, driven by a single sinusoidal signal. We used SPICE simulation to demonstrate the feasibility of our design.