Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

In this paper, degradation behaviors of bridged-grain (BG) polycrystalline silicon (poly-Si) thin-hlm transistors (TFTs) are systematically characterized and investigated. Device degradation exhibits a two-stage behavior, which is related to pulse falling time (t_f). A faster t_f brings a larger ON-current (I_ON) increase in the first stage and a larger I_ON decrease in the second stage. Electron trapping/injection into gate oxide and dynamic hot carrier effect are found to be responsible to ION increase in the hrst stage and I_ON decrease in the second stage, respectively. Compared with normal poly-Si TFTs, BG poly-Si TFTs show much more reliable performance under the same dynamic gate stress. The larger I_ON increase in the hrst stage in BG poly-Si TFTs is attributed to the enhanced vertical electric held in the channel near the gate oxide, while the much smaller I_ON decrease in the second stage is attributed to lateral electric held reduction caused by the sharing of the held across multiple reversely biased junctions inside the active channel. Incorporated with transient simulations, the degradation mechanisms for both the first stage and the second stage are elucidated. In addition, the impact of the hrst-stage degradation on the second-stage degradation is also clarified.

I. Introduction

Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have become one of the most promising candidates to integrate pixel elements with driver circuits to achieve the system-on-panel (SoP) applications [1], [2]. High-performance and high-reliable poly-Si TFTs are required to accomplish the above purpose. Unlike those in the pixels, TFTs in driver circuits are subjected to high-frequency () voltage pulses and suffer from dynamic degradation [3]. Therefore, poly-Si TFTs with superb dynamic reliability are desired. Dynamic-stress-induced degradation in poly-Si TFTs, mainly including dynamic-gate-stress-induced degradation [4]–[6] and dynamic-drain-stress-induced degradation [7]–[9], has been extensively investigated. Dynamic hot carrier (HC) effect [4]–[9], occurring during the pulse transient time, is found to be the dominant degradation mechanism in poly-Si TFTs. However, a few methods have been proposed to alleviate such dynamic-stress-induced degradation in poly-Si TFTs.