Toward an Efficient Multiview Display Processing Architecture for 3DTV

In this brief, we present an efficient architecture for multiview 3-D television (3DTV) processing. The architecture, which is designed for 4/8/9/16-compatible multiview 1080p and 4K displays, includes a frame memory controller, a parallel video scaling engine, and a subpixel rearrangement module for slanted lenticular displays. First, we observe and leverage computation locality in the viewpoint scaling problem, significantly reducing area and power overheads. Next, we propose an approximate formulation of the subpixel rearrangement computation, trading substantial computation energy for a small and analytically bounded error. Finally, we design a distributed data placement scheme that takes advantage of the inherent structured parallelism to amortize the cost of DRAM precharge cycles. Our proof-of-concept field-programmable gate array (FPGA) implementation is capable of processing frame-compatible streams in 1080p at 60 Hz and 4K at 30 Hz. Overall, the proposed optimizations lower the area by 2.75× for our FPGA implementation, and both area and power by 3.5× for an ASIC implementation.

I. Introduction

In order to provide compatibility with legacy 2-D systems, most existing multiview 3DTV systems are based on frame-compatible formats [1], [2]. In this format, taking a two-view format for example, the left and right views are first combined side by side (or top and bottom) in one image, and then encoded and transmitted as one frame; once each frame has been received and decoded, the left and right images are recovered and rescaled, and multiple views are synthesized by interpolating the two. Finally, each view is displayed in a set of subpixels, each of which is viewable from a specific angle through a fine lenticular overlay placed over the liquid crystal display [4].