A dynamic and low latency wireless NoC architecture

In this paper, we propose a novel wireless Network on Chip (NoC) architecture, which adopts a virtual hierarchical topology to achieve both low latency and power consumption. In this architecture, Radio Frequency Interconnect (RF-I) is used to establish the global network among routers. We also design a dynamic bandwidth allocation scheme to balance the network traffic, and an efficient multicast routing algorithm to increase the throughput. The simulation results show that our architecture can achieve at least 24.7% latency reduction and 17.8% power consumption saving compared with wired Mesh NoC.

1. Introduction

Irregular topologies, e.g. Butterfly Fat Tree (BFT) and De Bruijn graph, are usually featured by smaller network latency and lower power consumption in NoC design compared with Mesh topology [1]. However, restricted by the complicated VLSI implementation in conventional CMOS circuit, they are not popular used in wired NoCs. Radio Frequency Interconnect (RF-I) [2], in which randomly placed routers facilitate the implementation of all kinds of topologies, gives an opportunity to irregular topologies. RF-I also provides useful features, such as broadcasting and flexible bandwidth allocation ability for wireless NoCs.