A 7.5mW 35–70MHz 4th-order semi-passive charge-sharing band-pass filter with programmable bandwidth and 72dB stop-band rejection in 65nm CMOS

This paper proposes a highly reconfigurable charge-domain switched-gm-C biquad band-pass filter (BPF) topology that uses a semi-passive charge-sharing technique. It uses only switches, capacitors, digital circuitry for 3-phase non-overlapping clock generation and linearity-enhanced gm-stages. A 4_th-order BPF prototype operating at 1.2GS/s sampling rate is implemented using a cascade of two independent biquads in a 65nm LPE CMOS. A tunable center frequency of 35-70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The in-band 1-dB compression point is -2.4dBm, and the in-band IIP3 is +9dBm. The filter prototype consumes 7.5mW from a 1.2V supply, and occupies an active area of 0.17mm2.

I. Introduction

Flexible band-pass filters (BPFs) are key building blocks for channel selection filtering in wireless receivers, such as super-heterodyne, carrier aggregation, etc. The center frequency and bandwidth of the BPF are required to be widely tuned to support multi-standard operations. It is usually implemented using either an active-RC or a [1] architecture. The performance of such filters depends on the operational transconductance amplifier (OTA) used to implement the integrator. However, implementation of a high-quality OTA is increasingly challenging in deep sub-micron CMOS processes. Consequently, large power penalty is incurred to satisfy the performance requirements.