I. Introduction
Low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) fabricated using excimer laser crystallization (ELC) have been extensively investigated for use in active-matrix flat-panel displays (AMFPDs), system on panels (SOPs), and three-dimensional integrated circuits (3-D ICs) [1]–[4]. LTPS TFTs with the electron mobility exceeding 100 cm2/V-s have been realized using ELC in the super-lateral-growth (SLG) regime. However, random grain size distribution, random grain boundary location, and a narrow process window can lead to large variations in device performance, particularly in short-channel TFTs [4]–[6]. This has led to the development of several advanced ELC methods aimed at enlarging the grain size and assuming control over the location of grain boundaries. These methods include sequential lateral solidification (SLS), phase-modulated ELC (PMELC), -Czochralski process, and recessed-channel (RC) structure [3], [7]–[12]. Unfortunately, many of these methods involve complex fabrication process to form the designed film structure or are not readily attached to existing excimer laser annealing systems. Some of these methods have also proven problematic with regard to circuit layout, due to the anisotropic spacing of grain boundaries.