I. Introduction
The interest in employing FPGA-based reconfigurable systems in space applications is growing more and more [1]–[3]. Several reconfigurable systems are going to be launched in space in the next few years, e.g., the Polarimetric and Helioseismic Imager Data Processing Unit that will be hosted on the ESA Solar Orbiter [4] (launch planned in 2018) and the Fraunhofer On-Board Processor (FOBP) [5] (launch planned in 2020). These very expensive projects rely on high-end radiation-hardened mature FPGA devices with very high costs and lower performance compared with the latest commercial FPGAs. On the other hand, today's commercial SRAM-based FPGA devices represent the most interesting technological platform for research projects that need high performance and low cost at the same time. Such devices provide a significantly larger amount of resources and they can be dynamically and partially reconfigured, thus allowing performance increase, energy efficiency improvement, and fault tolerance enhancement [6]. Moreover, such devices are significantly cheaper than radiation hardened ones.