Inductance extraction for physics-based modeling of power net area fills with complex shapes and voids using the plane-pair PEEC method

Identifying the dominant inductance in power distribution network design for multi-layer printed circuit boards that use power net area fills is essential. The plane-Pair partial element equivalent circuit method is used herein to extract a lumped inductance suitable for a physics-based circuit model for power net area fills. The method is being applied for evaluating inductance for irregular geometry with cutouts and holes.

I. Introduction

The goal of power distribution network (PDN) design on a mutli-layer printed circuit board (PCB) is to reduce voltage ripple and droop on the power net below a specified value. Typically this is achieved in the design process by making the input impedance below a target value. The contribution to the inductance that dominates the PDN impedance includes three primary components, viz., the IC package vias connected to the power net, the decoupling capacitors vias connected to the power net, and the inductance across the power net area fill and its return as shown in Fig. 1. Fig. 1

Schematic representation of the PCB layout and current path for power delivery, and the associated inductance in each distinct portion.