Memory Servers for Multicore Systems

In multicore systems, tasks can be significantly delayed due to contention for access to shared physical resources. Due to the complexity of the underlying hardware arbitration, analyzing resources such as DRAM main memory is challenging. In particular, compositional delay bounds tend to be highly pessimistic, while non- compositional bounds are tighter but prevent independent subsystem development. To address this issue, in this paper we introduce a novel memory server for multicore real-time systems under partitioned fixed-priority scheduling. Similar to a hierarchical server, our memory server regulates the amount of resource (bandwidth) that a group of tasks is allowed to consume, but the server interface is modified to account for the properties of delay analysis. We show how to derive schedulability conditions for each server and for the system as a whole. Our technique can support multiple memory regulation implementations and delay analyses, while significantly improving system schedulability compared to the unregulated case.

I. Introduction

In multicore systems, tasks can be significantly delayed due to contention for access to shared physical resources such as caches, interconnections and main memory. In memory intensive systems, DRAM main memory is often the main bottleneck [35], [40]. For this reason, a significant amount of effort has been devoted to analyze and control the impact of memory sharing. One way to address the problem is adopting real-time DRAM controllers [22], [1], [9], [25], [7], [34], [17], which offer certain timing guarantees in accessing DRAM by hardware design. However, such hardware approaches are not available on COTS systems.