A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

I. Introduction

Metal–oxide resistive random access memory (RRAM) is a competitive emerging memory candidate, as it offers the potential for high storage density (, fast speed ( ns), and low energy consumption (<pJ) [1]–[4]. Extensive research has been conducted to improve the device performance and understand the resistive switching mechanisms [5], leading to interest in exploring possible applications. The array sizes demonstrated have been increasing [5], reaching 32 Gb in 2013 [6]. At the same time, several 3-D RRAM concepts have been reported [7]–[9], providing possible solutions to complement ultrahigh density 3-D NAND [10]. Beyond the traditional data storage, various RRAM applications have been reported, such as using RRAM devices in neuromorphic systems, ternary content-addressable-memory (TCAM), and nonvolatile SRAM [11]–[16]. To satisfy the increasing need for the explorations of circuit- and system-level RRAM applications, several circuit-compatible analytical models have been developed. Yu et al. [12] and Guan et al. [17] employed a 1-D filament simplification, where the tunneling gap growth reflects the resistance change during programming. Bocquet et al. [18] and Noh et al. [19] used the filament diameter to capture different resistance states. Huang et al. [20] and Li et al. [21] took 2-D filament growth into account during the SET process. To deal with the inherent variability in RRAM devices, we have developed and made available in the public domain [22], an RRAM model that is implemented in Verilog-A and can be executed in the circuit simulator SPICE.