Field-Plated Ga2O3 MOSFETs With a Breakdown Voltage of Over 750 V

Depletion-mode field-plated Ga₂O₃ metal–oxide–semiconductor field-effect transistors were demonstrated for the first time. Substantial enhancement in breakdown voltage was achieved with a gate-connected field plate. The device channels, formed by selective-area Si ion implantation doping of an undoped Ga₂O₃ epilayer, were electrically isolated by the highly resistive epilayer without mesa etching. Effective surface passivation and high Ga₂O₃ material quality contributed to the absence of drain current collapse. The transistors exhibited an off-state breakdown voltage of 755 V, a high drain current on/off ratio of over $10^{9}$ , and stable high temperature operation against 300°C thermal stress.

I. Introduction

Gallium oxide (Ga₂O₃) – with a wide bandgap of 4.5 to 4.9 eV [1]–[3] and the availability of economical device-quality native substrates – is a strong contender for future power devices including Schottky barrier diodes [4], [5] and field-effect transistors [6]. A Si-ion (Si⁺) implantation doping technique for fabricating single-crystal -Ga₂O₃ metal-oxide-semiconductor field-effect transistors (MOSFETs) on unintentionally-doped (UID) epilayers has been established to realize low contact resistance and reliable channel conductivity [7], leading to promising device characteristics such as a three-terminal off-state breakdown voltage ( of 415 V and a drain current ( on/off ratio of [8], [9]. The unmanaged high electric field in the gate-drain depletion region of those devices has, however, undermined their potential and rendered them susceptible to reliability concerns, notably premature impact ionization breakdown and surface charging with associated degradation in switching performance. This work presents the first demonstration of depletion-mode single-crystal Ga₂O₃ field-plated MOSFETs (FP-MOSFETs) that addressed the aforementioned challenges. The was substantially increased by employing a gate-connected FP, which was designed with the support of device simulations. A SiO₂ dielectric was used to serve a dual functionality for FP mechanical support as well as device surface passivation. The high resistivity of UID Ga₂O₃ grown by molecular beam epitaxy (MBE) was harnessed for effective planar device isolation without mesa etching to overcome the necessity for a circular device geometry previously adopted. The FP-MOSFETs exhibited a of 755 V, an on/off ratio of over , and normal high temperature operation at 300°C.