I. Introduction
In the short-range wireless applications such as autonomous wireless sensor network, low voltage and low power consumption transceivers are highly required to conserve the longer battery life. Since the largest portion of total dc power dissipation in transceiver occurs at the power amplifier (P A), the high-efficiency performance is very crucial. However, reducing the supply voltage without degrading the efficiency is very challenging. Several topologies were reported to achieve high efficiency performance at low voltage operations [1]–[6]. The power amplifier in [1] proposed a parallel amplification to realize high efficiency performance at supply voltage of 1.5 V. This technique, however, requires large chip size due to utilization of large LC balun as parallel combiners. Although injection-locking technique in [2] achieves high gain and high efficiency at low supply voltage, the circuit was complicated.