Effects of Parasitic Resistance on the Performance of Silicon Avalanche Photodetectors in Standard CMOS Technology

We investigate the effects of parasitic resistance on the performance of silicon avalanche photodetectors (APDs) fabricated in the standard complementary metal-oxide-semiconductor (CMOS) technology. Two types of CMOS-APDs based on the P⁺/N-well junction having two different parasitic resistances are realized, and their current-voltage characteristics, responsivities, avalanche gains, photodetection frequency responses, and electrical reflection coefficients are measured and compared. In addition, the effect of parasitic resistance on the photodetection bandwidth is analyzed with an equivalent circuit model. It is clearly demonstrated that the parasitic resistance has great effects on the gain and photodetection bandwidth of CMOS-APDs.

I. Introduction

Development and implementation of photonic devices in complementary metal-oxide-semiconductor (CMOS) technology have drawn considerable attention in recent years because they can provide monolithic integration of photonic devices with CMOS circuits for greatly enhanced functionality with a competitive price across a wide spectrum of applications. In particular, CMOS-compatible avalanche photodetectors (CMOS-APDs) are of great interest for several applications ranging from optical interconnects to image sensors [1]–[3]. Since the standard CMOS technology does not provide the optimal fabrication processes for APDs, there have been great research interests in improving and optimizing the performance of the APDs based on available processes in CMOS technology. Structures for PN junctions and guard rings as well as front-end-of-line (FEOL) design issues have been investigated [4]–[7]. However, there have been no reports on the effects of parasitic resistance, which heavily depends on back-end-of-line (BEOL) designs, on the performance of CMOS-APDs.