2D Semiconductor FETs—Projections and Design for Sub-10 nm VLSI

Two-dimensional (2D) crystal semiconductors, such as the well-known molybdenum disulfide (MoS₂), are witnessing an explosion in research activities due to their apparent potential for various electronic and optoelectronic applications. In this paper, dissipative quantum transport simulations using nonequilibrium Green's function formalism are performed to rigorously evaluate the scalability and performance of monolayer/multilayer 2D semiconductor-based FETs for sub-10 nm gate length very large-scale integration (VLSI) technologies. Device design considerations in terms of the choice of prospective 2D material/structure/technology to fulfill sub-10 nm International Technology Roadmap for Semiconductors (ITRS) requirements are analyzed. First, it is found that MoS₂ FETs can meet high-performance (HP) requirement up to 6.6 nm gate length using bilayer MoS₂ as the channel material, while low-standby-power (LSTP) requirements present significant challenges for all sub-10 nm gate lengths. Second, by studying the effects of underlap (UL) structures, scattering strength, and carrier effective mass, it is found that the high mobility and suitably low effective mass of tungsten diselenide (WSe₂), aided by the UL, enable 2D FETs for both HP and LSTP applications at the smallest foreseeable (5.9 nm) gate length. Finally, possible solutions for sub-5 nm gate lengths, specifically anisotropic 2D semiconductor materials for HP and sub-kT/q switch (2D tunnel FET) for LSTP, are also proposed based on the effects of critical material parameters on the device performance.

I. Introduction

The atomic scale thicknesses of 2D semiconductors offer high scalability to FETs using them as channel materials, which is the primary motivation for researchers to explore them for the FET application in sub-10 nm nodes [1], [2]. Although conventional bulk semiconductors, such as silicon and germanium, can also be made very thin, 2D semiconductors own extra advantages, specifically, atomically smooth and dangling bond-free surface, and uniform and fixed (with the number of layers) thickness, as schematically shown in Fig. 1(a) and (b). These advantages intrinsically suppress possible trap generation, carrier scattering, and thickness (and hence bandgap) variation, guaranteeing robust device performance. By comparing the carrier mobilities in molyb-denum disulfide (MoS₂) [3], [4], the most widely studied 2D semiconductor, and in the mainstream Si [5] during thickness scaling, as shown in Fig. 1(c), it is found that the mobility degradation rate with decreasing thickness in MoS₂ is much slower with respect to that in Si, leading to higher mobility at the extremely scaled (monolayer or 1L) thickness. With continuous improvement in material quality, and proper gate dielectric engineering, the mobilities in MoS₂ and other 2D materials can be further improved, as recently demonstrated in [6] with the mobility in monolayer MoS₂ boosted to 44 cm²/ [see Fig. 1(c)]. Note that the FET channel thickness scaling is imposed by gate length scaling as reflected by a general scaling formula [7], [8], where is the minimum gate length in order to maintain good device electrostatics, is a constant that generally should be is the channel (gate oxide) thickness, and is the dielectric constant of channel (gate oxide). The ultrasmall of 2D semiconductors enable ultrasmall of 2D FETs. Fig. 1.

(a) Issues of bulk material during thickness scaling for FET application. (b) Advantages of 2D materials over bulk materials. (c) Carrier mobility degradation with reduced material thickness for Si and MoS₂. An improved mobility recently achieved in monolayer (1L) MoS₂ with thickness of 0.65 nm is also included. (d) Schematic of a DG 2D FET.