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Threshold voltage extraction circuit for low voltage CMOS design using basic long-channel MOSFET | IEEE Conference Publication | IEEE Xplore

Threshold voltage extraction circuit for low voltage CMOS design using basic long-channel MOSFET


Abstract:

The threshold voltage (Vth) is a key parameter in MOSFET design and modeling. There are many definitions and extraction methods, each one given with a focus on different ...Show More

Abstract:

The threshold voltage (Vth) is a key parameter in MOSFET design and modeling. There are many definitions and extraction methods, each one given with a focus on different aspects. This work presents a simple circuit that extracts the threshold voltage under low voltage conditions and using a feedback loop in order to reach supply independence. The circuit has been simulated using the BSIM3v3 model for a 0.18µm CMOS process. The extracted value of VTHN is very close to the model nominal value (VTHO) used from the model parameters being the variation of +0.327% and −0.294% from VDD=0.6V to VDD=3V. The bias current I is from 810.7nA to 872nA for the same supply voltage variation.
Date of Conference: 24-27 February 2015
Date Added to IEEE Xplore: 10 September 2015
ISBN Information:
Conference Location: Montevideo, Uruguay
References is not available for this document.

I. Introduction

The threshold voltage is a fundamental parameter for MOSFET modeling and characterization, which represents the start of significant drain current flow. It has been given several definitions [1], but it may be essentially understood as the gate voltage value at which the transition between weak and strong inversion takes place in the channel of the inversion-type MOSFET [2].

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1.
A. Ortiz-Conde, F. J. Garcia-Sánchez, J. J. Liou, A. Cerdeira, M. Estrada and Y. Yue, "A review of recent MOSFET threshold voltage extraction method", Microelectronics Reliability, vol. 42, pp. 583-596, 2002.
2.
X. Zhou, K. Y. Lim and D. Lim, "A Simple and Unambiguous Definition of Threshold Voltage and Its Implications in Deep-submicron MOS Device Modeling", IEEE Transactions on Electron Devices, vol. 46, no. 4, April 1999.
3.
Grey, Hurst, Lewis and Meyer, "Analysis and design of analog integrated circuits" in , John Wiley Sons, 2001.
4.
Z. Wang, "Automatic VT extractors based on an nxn2 MOS transistor array and their application", IEEE J. Solid-State Circuits, vol. 27, no. 9, pp. 1277-1285, Sept. 1992.
5.
I. M. Filanovsky, "Input-free VTP and-VTN extractor circuits realized on the same chip", Analog Integrated Circuits and Signal Processing, vol. 19, pp. 151-157, 1999.
6.
Fred Thomas and W. Timothy Holman, "MOSFET threshold voltage extractor circuits based on square-law behavior", 42nd Midwest Symposium on Circuits and Systems MWSCAS, pp. 1118-1121, 1999.
7.
G. Fikos and S. Siskos, "Low-voltage low-power accurate CMOS VT extractor", IEEE Transactions on Circuits and Systems-II, vol. 48, no. 6, pp. 626-628, 2001.
8.
Y. Wang and G. Tarr, "Input-free cascode Vthn and Vthp extractor circuits", Proceedings of the 11th IEEE International Conference on Electronics Circuits and Systems (ICECS 2004), pp. 282-285, Dec. 2004.
9.
S. Sengupta, "An input-free NMOS VT extractor circuit in presence of body effects", Proc. IEEE International Symposium on Circuits and Systems ISCAS, pp. I–912-I–915, 2004.
10.
S. Vlassis and C. Psychalinos, "Low-voltage CMOS VT extractor", Electronics Letters, vol. 43, no. 17, August 2007.
11.
Jaime Ramirez-Angulo, Venkata Sailaja Kasaraneni, Ramón G. Carvajal and Antonio J. López-Martin, "Simple Low Voltage Low Power Implementations of Circuits for VT Extraction", 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 233-236, 2010.

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References

References is not available for this document.