Printable depolarizing chipless RFID tag based on DGS resonators for suppressing the clutter effects

In this paper, a novel Frequency Coded (FC) depolarizing chipless Radio Frequency Identification (RFID) tag is introduced. The uniplanar tag consists of L-shape Defected Ground Structure (DGS) resonators defining the tag signature and two orthogonally polarized Ultra Wideband (UWB) monopole antennas for realizing the cross-polarization retransmission process. Consequently, the polarization diversity at the reader and tag utilized to reduce the mutual coupling, suppress the channel clutter effects and efficiently detect the tag on different platforms. Furthermore, the number of notches in the presented tag could be easily increased by adding parallel resonators. This significantly enable increasing the coding capacity while preserving the same tag size. Besides, the tag structure is printable, symmetrical and easily encoded. An 8-bit code prototype from (3.1 GHz to 6.1 GHz) is presented and the maximum readable number of notches will be investigated. The enhancement in the developed design with respect to the recent chipless RFID tags will be discussed. The UWB monopole antenna and the DGS resonators simulation, implementation and measurement are separately demonstrated. The manufactured chipless RFID tag operation is conclusively verified in indoor real-world environment.

I. Introduction

Radio Frequency Identification(RFID) principle is the use of RF signals for access of information on the tags attached on objects. RFID system consists of two major hardware components: a transponder/tag containing an EM physical signature used for identification of an object and the interrogator/reader for collecting data from tags. RFID tags allow for automated tracking, as well as long range and non-sight-of-light reading. Presently, chipless RFID tags have become an important research topic due to the massive business potential in item-level tracking applications. To realize such item-level tags, however, a few technical challenges have to be solved, such as reducing fabrication cost, improving coding capacity, shrinking geometries, enabling re-reconfigurability of ID generating circuits, as so on. To minimize cost, efforts have to be made to reduce the size of such tags as the size increases with increasing number of bit capacity.