System-Level Modeling for Transient Electrostatic Discharge Simulation

This paper introduces an improved electrostatic discharge (ESD) system-level transient simulation modeling method and discusses its validation using IEC 61000-4-2 ESD pulses on a real-world product. The system model is composed of high current and broadband (up to 3 GHz) models of R, L, C, ferrite beads, diodes, and integrated circuit IO pins. A complex return path model is the key to correctly model the system's response to the IEC excitation. The model includes energy-limited time-dependent IC damage models. A power-time integral method is introduced to accurately determine if a junction would experience thermal runaway under an arbitrary injection waveform. The proposed method does not require knowledge of the junction's microscopic geometry, material information, defect location, or melting temperature.

I. Introduction

Recent studies have shown that system-level electrostatic discharge (ESD) simulation can serve as a powerful tool for analyzing ESD performance [1]. The simulation enables the design of reliable protection on the first attempt and avoids the need for repeated design optimization tests.