Design and simulation of a high performance dopingless p-tunnel field effect transistor

In this paper, we propose a novel p-type dopingless tunnel field effect transistor (DL-p-TFET). The proposed DL-p-TFET device does not use conventional ion implantation or diffusion for realizing source and drain regions; these regions are created by using metals of different work function, a charge plasma concept. It has been observed that by optimizing the source and gate electrode gap (L_{gap, S}) and oxide thickness under source electrode (T_{oxide, S}) in the proposed DL-p-TFET device, better performance can be obtained in comparison to the conventional doped p-TFET (D-p-TFET). The 2D simulation study has shown a significant improvement in ON current (I_on), cutoff frequency (f_T) and subthreshold slope (SS) in the proposed device in comparison to the conventional D-p-TFET. It is found observed that the I_ON, f_T and SS in the proposed DL-p-TFET are increased by 156%, 2.5% and 133%, respectively, in comparison to the conventional D-p-TFET. Since the proposed device is dopingless, it is free from random dopant fluctuations issues and can be processed at low temperatures.

I. Introduction

The scaling of MOSFET has resulted in a significant enhancement in speed and functionality, reduction in power dissipation and is an important factor for enhancing the validity of Moore's law further and further. However, MOSFET scaling is nearing its end; it is extremely difficult to extract high performance out of scaling now. The scaling of devices below 32 nm technology node is challenging and a lot of short channel effects hamper scaling below 32 nm [1]–[2]. The main issue which hampers scaling below 32 nm node is the limitation in reducing the supply voltage [2] and significant increase in leakage current. Further, the highly scaled doped devices face severe issues of random dopant fluctuations [3]. The supply voltage can be reduced further without facing the performance loss, particularly increase in leakage current, if the subthreshold slope of the device is being reduced. However, the subthreshold slope (SS) of the MOSFET is limited to −60 mV/decade and cannot be reduced further.