Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches

We propose a design technique for embedding read-only memory (ROM) in spin-transfer torque MRAM (STT-MRAM) arrays by adding an extra bit-line in every column of the array. RAM and ROM data, which can be different, are stored in the same bitcell and the ROM capacity may be as large as the RAM capacity. Furthermore, our proposed ROM-embedding technique is applicable to any resistive memory technology in which the bit-cell topology is identical to that of the STT-MRAM bit-cell. An additional sense amplifier is required in the peripheral circuitry, hence we propose an area-optimized peripheral circuitry to minimize the total area penalty of embedding ROM. Our analysis reveals that the ROM may be embedded in the STT-MRAM array without area overhead and without any penalty in the performance of the memory as RAM. Furthermore, our simulations show that the embedded ROM may be used to accelerate applications that use lookup tables with as much as 30% improvement in instructions per cycle of a processor using ROM-embedded STT-MRAM for its L2 cache.

I. Introduction

Many applications, such as digital signal processing, math libraries, and on-chip built-in self-test, use data that are determined at design time and stay constant during runtime (which we refer to as static data). Static data may be stored as lookup tables in on-chip read-only memory (ROM). However, storing large amounts of static data in on-chip ROM incurs significant area and power overheads. An alternative method is used to store static data off-chip. In this case, the processor has to fetch the required static data into on-chip cache during program execution, which leads to performance degradation. The problem is further exacerbated when data for each program running concurrently are mapped to the same cache location (also called cache thrashing). The static data used by a program may need to be evicted from cache as a result and the processor has to fetch the evicted data from off-chip memory again in order to continue program execution. Hence, realizing an on-chip ROM with minimal overhead allows static data to be stored closer to the processor, and may be used to accelerate the execution of applications.