Optimal design of second generation current conveyors by the Artificial Bee Colony technique

The field of metaheuristics based on swarm intelligence (SI) techniques, for the application to analog design optimization is a rapidly growing domain of research. This is due to the importance of these metaheuristics to solve NP-hard problem. The main goal of this paper is to use the Artificial Bees Colony (ABC) technique to the optimal sizing of analog circuits. The paper details the proposed algorithm and highlights its performances using some mathematical test functions. An application to the optimal sizing of CMOS second generation current conveyors (CCII) for specific performances is presented, and comparison results with published works are highlighted. SPICE simulation results are given to show the viability of the suggested algorithm.

I. Introduction

Integrated circuit design is a delicate and complicated process activity due to the number of variables involved, the number of required objectives to be optimized and the constraint of functions restrictions. Generally, the circuit sizing is carried out thanks to the experiment and the intuition of the designer or according to the approaches based on fixed topologies and/or statistical techniques [1]. However, these techniques are time consuming and do not guarantee achieving the global optimum solution.