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Floating-gate CMOS analog memory cell array | IEEE Conference Publication | IEEE Xplore

Floating-gate CMOS analog memory cell array


Abstract:

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are store...Show More

Abstract:

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off chip. Moving parameter storage on chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip non-volatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We achieve greater than 13-bit precision with no crosstalk between memory cells.
Date of Conference: 31 May 1998 - 03 June 1998
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-4455-3
Conference Location: Monterey, CA, USA

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